1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit having an input protection circuit for discharging a surge voltage such as an overvoltage caused by for example a static electricity applied to an external terminal, to a power supply voltage node or a ground potential node.
2. Description of Related Art
Examples of the prior art input protection circuit used for an input protection of a semiconductor integrated circuit (LSI), will be described with FIGS. 1, 2, 3A and 3B. FIG. 1 is a circuit diagram illustrating one example of the prior art input protection circuit, which will be called a first prior art example. As shown in FIG. 1, this input protection circuit includes a p-channel MOS field effect transistor (called a "pMOS transistor" hereinafter) QP3 as a protecting element for discharging a current to a power supply voltage side. This pMOS transistor QP3 is connected in the form of a diode in which a gate and a source are connected to each other. The source and the gate of the pMOS transistor QP3 are connected in common to a power supply voltage line 1, and a drain of the pMOS transistor QP3 is connected to an external input terminal 7. The input protection circuit also includes an n-channel MOS field effect transistor (called an "nMOS transistor" hereinafter) QN4 as a protecting element for discharging a current to a ground potential side. This nMOS transistor QN4 is also connected in the form of a diode in which a gate and a source are connected to each other. The source and the gate of the nMOS transistor QN4 are connected in common to a ground line 2, and a drain of the nMOS transistor QN4 is connected to the external input terminal 7.
In the shown example of the LSI, an input first stage circuit 5 is constituted of a CMOS inverter formed of a pMOS transistor QP1 and an nMOS transistor QN2. An input node of this inverter (namely, common-connected gates of QP1 and QN2) is connected through a resistor R5 to a connection node N1 between the above mentioned two protecting elements QP3 and QN4. An output signal of the input first stage inverter 5 is supplied an internal circuit 3 where the signal is processed. This internal circuit 3 executes a signal processing which is an object of the LSI. Incidentally, this LSI is manufactured by a so-called silicon gate process, and therefore, gate electrodes of not only the MOS transistors QP1, QN2, QP3, QN4 but also MOS transistors constituting logic gates included in the internal circuit, are formed of polysilicon. In addition, the resistor R5 is also formed of polysilicon, and is formed at the same time as formation of the gate electrodes of the MOS transistors.
FIG. 2 is a circuit diagram illustrating another example of the prior art input protection circuit, which will be called a second prior art example. As shown in FIG. 2, this input protection circuit is different from the first prior art example in that an nMOS transistor QN5 is used as a power supply voltage side protecting element. This protecting transistor QN5 has a source connected to the power supply voltage line 1, a drain connected to the input terminal 7 and a gate connected to the ground line 2. On the other hand, as the ground potential side protecting element, the nMOS transistor QN4 is provided similarly to the first prior art example. This nMOS transistor QN4 is connected in the form of a diode in which a gate and a source are connected to each other. The source and the gate of the nMOS transistor QN4 are connected in common to the ground line 2, and a drain of the nMOS transistor QN4 is connected to the external input terminal 7.
In this shown example of the LSI, an input first stage circuit 5 is constituted of a CMOS inverter formed of a pMOS transistor QP1 and an nMOS transistor QN2. An input node of this inverter is connected through a resistor R5 to a connection node N1 between the above mentioned two protecting elements QN5 and QN4.
In the input protection circuits of the above mentioned first and second prior art examples, when a surge voltage caused by for example a static electricity is applied to the input terminal 7, the polysilicon resistor R5 dulls or damps the waveform of the surge voltage. With this damping action, an abrupt surge voltage is prevented from being directly applied to the gates of the pMOS transistor QP1 and the nMOS transistor QN2 which constitute the input first stage inverter 5. On the other hand, the pMOS transistor QP3 or the nMOS transistor QN5 causes a breakdown or punch-through so as to create a current path leading to the power supply voltage line 1, so that the current is discharged to the power supply voltage line 1. Alternatively, the nMOS transistor QN4 causes a breakdown or punch-through so as to create a current path leading to the ground line 2, so that the current is discharged to the ground line 2.
In the input protection circuits of the first and second prior art examples, thus, the gate oxide film of the MOS transistors in the input first stage inverter 5 is prevented from being destroyed by action of the above mentioned two actions (namely, the damping of the surge voltage waveform and the creation of the surge current discharging path).
Now, referring to FIG. 3A, there is shown a layout pattern diagram illustrating a third example of the prior art input protection circuit, which will be called a third prior art example. This third prior art example is an input protection circuit using a common discharging line. As shown in FIG. 3A, this input protection circuit for the LSI is so configured that when a surge voltage is applied to an input terminal 7, a current path is created to extend from the input terminal 7 through an input protection circuit 21 to a scribing line 24.
This scribing line 24 is a line partitioning chips on a wafer, and when the wafer is divided into chips, a cutting line is formed by a dicer along the scribing line and the wafer is divided along the cutting line. Ordinarily, the scribing line is covered with aluminum film and is conducting with a silicon substrate. The prior art input protection circuit 21 is constituted of a lateral NPN bipolar transistor formed of two n+ diffused layers 26 and 27 and a p-type silicon substrate 29 and a PN junction diode formed of the n.sup.+ diffused layer 26, the p-type silicon substrate 29 and a p+ diffused layer 25. Now, assuming that a surge voltage is applied to the input terminal 7, the current path from the input terminal 7 to the scribing line 24 is created by the lateral bipolar transistor and the forward direction diode of the input protection circuit 21.
Referring to FIG. 3B, there is shown a layout diagram illustrating how the third prior art input protection circuit is located on a semiconductor chip. As shown in FIG. 3B, the protection circuits 21 are located to the scribing line 24 constituting the common discharging line, nearer than the terminals 7 to the scribing line 24. This is for the purpose of making the resistance of the discharging path created through the input protection circuit 21 as small as possible, so as to easily discharge the current.
However, in the above mentioned prior examples, a first problem is encountered in which, when the surge voltage is applied to the input terminal, in order to discharge the current from the input terminal, there are required two discharging paths, namely, the path for discharging the current to the power supply voltage line 1 and the path for discharging the current to the ground line. Therefore, there are required at least two elements for causing the breakdown or punch-through, such as the MOS transistors QP3, QN4 and QN5 in FIGS. 1 and 2. As a result, the input protection circuit inevitably becomes large, and therefore, a necessary chip area increases.
Furthermore, a second problem is encountered in which with the increase of the area of the input protection circuit, a diffused layer capacitance and a gate capacitance of the input protecting elements become large, so that the input terminal capacitance correspondingly becomes large.
A third problem is encountered in which, in order to make the resistance of the discharging path created in the input protection circuit as small as possible so as to easily discharge the current, such a restriction that the protection circuits must be located near to the power supply voltage line or the ground line, is added to a circuit layout.